Making the Industry's First 64 Gbps UCIe IP Follows the Successful Tapeout of Alphawave Semi's Gen2 36 Gbps UCIe IP on TSMC's 3nm Technology, Supporting Both High-Yield, Low-Cost-Low -Cost Organic Substrate Standard Packaging (NYSE:) and Advanced Packaging Technologies.
LONDON & TORONTO–( BUSINESS WIRE )–Alphawave Semi (LSE: AWE ), a world leader in high-speed interconnect and silicon computing for the global technology infrastructure, proudly introduces the first 64 Gbps Universal Chiplet Interconnect Express (UCIe™) ) Die-to-Die (D2D) IP Subsystem to deliver unprecedented data connection chiplet rates, setting a new standard of ultra-high-performance D2D communication solutions in the industry. The third generation, 64 Gbps IP Subsystem builds on the achievements of the recent Gen2 36 Gbps IP subsystem and the proven silicon of the Gen1 24 Gbps and is available in TSMC's 3nm Technology for Medium and High-end packaging. Proven silicon success and tapeout milestones pave the way for Alphawave Semi's Gen3 UCIe™ IP subsystem offering.
Alphawave Semi is set to revolutionize connectivity with its Gen3 64 Gbps UCIe IP, delivering a maximum bandwidth of more than 20 Tbps/mm, with low power and latency. This solution is highly configured to support multiple protocols, including AXI-4, AXI-S, CXS, CHI and CHI-C2C to address the growing demands for high performance connectivity in integrated systems in High-Performance Computing (HPC ), Data Centers, and Artificial Intelligence (AI) applications.
The design conforms to the latest UCIe™ Specification and has a rapid architecture with advanced test features, including monitoring the health of each channel, creating a robust foundation and enabling an open and interactive chiplet system.
The UCIe D2D interface facilitates a series of standard chiplet connections. Common uses include integrating low-latency compass chiplets, parallel connectivity using UCIe power delivery, and integrating compute into I/O chiplets using UCIe interfaces and PCIe, the CXL, or Ethernet. In addition, optical timers can leverage the UCIe chiplet architecture to establish reliable, low-latency optical I/O links through optical engines, improving off-system communication. This supports the development of low-power, high-speed solutions for data centers and AI/ML systems.
For high-performance applications, creating a standard HBM die using the latest UCIe standard is a cutting-edge method that involves tightly integrating memory dies and compute dies to achieve very high bandwidth and low latency between components. This allows reuse of existing die-to-die shoreline on the main die for core-to-core or core-to-I/O connections. This method greatly improves memory transfer in AI applications where low power and reduced latency distinguish performance.
The UCIe Consortium is pleased to see members achieving important metrics such as tapeouts, which demonstrate the growing acceptance of the UCIe Specification, said Brian Rea, Chair of the UCIe Consortium Marketing Work Group. UCIe is a cornerstone of the chiplet industry, providing a robust solution for high-speed, low-latency die-to-die interconnects. By embracing open standards, we empower the industry to accelerate innovation, reduce time to market, and deliver breakthrough technology.
“Our successful Gen2 UCIe™ IP tapeout at 36 Gbps on 3nm technology builds on our proven silicon 3nm UCIe IP and CoWoS ® packaging,” said Mohit Gupta, senior VP and and GM, Custom Silicon and IP, Alphawave Semi. “This achievement puts our Gen3 UCIe IP standard at 64 Gbps, which is targeted to deliver high-performance, 20 Tbps/mm performance to our customers who need increased bandwidth for critical AI bandwidth needs by 2025.
This achievement, alongside Alphawave Semi's industry-first 3nm silicon-certified Gen1 UCIe IP, confirms the company's rapid progress as a leader in high-performance chiplet communications solutions with a full suite of silicon-certified IP communication subsystems hyperscaler and data-infrastructure. markets.
Learn more:
- Get Alphawave Semi's UCie™ IP solutions.
- Read our The latest release is the industry's first silicon-proven 3nm UCIe™ IP.
- Check out our Multi-protocol chiplet release.
- Watch the DAC 2024 video: From Simulation to Silicon: Alphawave & Keysight's UCIe™ Validation.
- Read our blog: Redefining XPU Memory for AI data centers with custom HBM.
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About Alphawave Semi
Alphawave Semi is a world leader in high-speed connectivity and silicon computing infrastructure for global technology. To deal with the exponential growth of data, Alphawave Semi technology services are an essential requirement: it allows data to move quickly, reliably, and with high performance at low power. We are an integrated semiconductor company, and our IP, custom silicon, and connectivity products are delivered by tier-one global customers in data centers, computing, networking, AI, 6G/5G, autonomous vehicles , and maintenance. Founded in 2017 by a team of expert professionals with a proven track record in semiconductor IP licensing, our goal is to accelerate the critical infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com.
Alphawave Semi and the Alphawave Semi logo are trademarks of Alphawave IP Group plc. All rights reserved.
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Claudia Cano-Manuel
Grand Bridges Marketing Limited
press@awavesemi.com
+44 7562 182327
Source: Alphawave Semi